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Architecture

Concepts

  • MSHR: miss status holding registers. Hardware to handle cache misses; allow cpu to continue execution while a miss is handled.

Discussion on Accelerators 3/7

CPU reaches a limit, specialized hw is a way out.

Big pages for data intensive applications. Less checking. Application even does not need to know. Heap knows how much data is allocated. Just use a smart heap to determine a bigger page size for data.

48 bits for PA. 16 bits are not used. Check the protection.

[ 16 | 28 | 20 ] // 64 bits

page size is 2^20 = 1MB. If 1MB page, 36 bits can be used, which is 2^6 = 64GB memory. So the remaining 28 bits can be used.